A 0.9 pJ/bit, 12.8 GByte/s WideIO memory interface in a 3D-IC NoC-based MPSoC

3D Integrated Circuit (3D-IC) opens architecture opportunities for improved SoC-to-memory interconnect bandwidth between dies. This paper presents the design of a two-tier 3D-IC composed of one NoC-based MPSoC and one multi-channel WideIO mobile SDRAM stacked in a face-to-back configuration. Measure...

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Bibliographische Detailangaben
Hauptverfasser:	Dutoit, Denis, Bernard, Christian, Cheramy, Severine, Clermidy, Fabien, Thonnart, Yvain, Vivet, Pascal, Freund, Christian, Guerin, Vincent, Guilhot, Stephane, Lecomte, Stephane, Qualizza, Gianni, Pruvost, Julien, Dodo, Yves, Hotelier, Nicolas, Michailos, Jean
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Bandwidth Integrated circuit interconnections Memory management Mobile communication Random access memory System-on-chip
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Beschreibung
Zusammenfassung:	3D Integrated Circuit (3D-IC) opens architecture opportunities for improved SoC-to-memory interconnect bandwidth between dies. This paper presents the design of a two-tier 3D-IC composed of one NoC-based MPSoC and one multi-channel WideIO mobile SDRAM stacked in a face-to-back configuration. Measurements of the 3D-IC show that the targeted 12.8 GByte/s bandwidth is achieved in worst case conditions, while offering a 0.9 pJ/bit 3D I/O link power efficiency.
ISSN:	0743-1562