A VCO linearization system for ADC applications

Time-domain ADCs are increasing in popularity due in part to compatibility with deep sub-micron (DSM) CMOS technology. The performance of time-domain ADCs that use VCOs in open loop is to a large extent limited by the linearity of the output frequency of the VCO as a function of its control voltage. In this paper, we present an analysis of a system for VCO linearization, suppressing distortion and phase noise introduced by the VCO. We connect the noise from each component of the system to the performance of the ADC. Further, we demonstrate the feasibility of the system with transistor level simulations. We designed the simulated system for 12 bit linearity and simulated the transistor level model using a commercially available 90 nm CMOS process design kit (PDK).