Study of threshold voltage of p-channel four gate transistor

Study of threshold voltage of p-channel four gate transistor

A three dimensional model of SOI p-channel four gate transistor has been developed using device simulator Silvaco/ATLAS. Threshold voltage for the device is studied for different biasing condition at the four gates and different physical parameter like channel length. The results are compared to the...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: Noor, Samantha Lubaba, Haq, A. F. M. Saniul, Hassan, Muhsiul
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Analytical models
Electric potential
Four Gate Transistor
Fully Depleted
Junctions
Logic gates
Numerical models
SOI
Threshold voltage
Transistors
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Beschreibung
Zusammenfassung:A three dimensional model of SOI p-channel four gate transistor has been developed using device simulator Silvaco/ATLAS. Threshold voltage for the device is studied for different biasing condition at the four gates and different physical parameter like channel length. The results are compared to the results obtained from the analytical model of threshold voltage of n-channel four gate transistor to find out whether the analytical model works for p-channel G 4 -FET also.
DOI:10.1109/ICIEV.2013.6572568