A 10MHz-BW, 5.6mW, 70dB SNDR ΔΣ ADC using VCO-based integrators with intrinsic DEM
This paper presents the design of a first-order close-loop VCO based ΔΣ ADC. Unlike other VCO based ADC, it does not contain operational amplifier which is power hungry and scaling unfriendly. Also, by using two VCOs referring to each other, it has an intrinsic DEM capability that improves SNDR degr...
Gespeichert in:
| Hauptverfasser: | , , |
|---|---|
| Format: | Tagungsbericht |
| Sprache: | eng |
| Schlagworte: | |
| Online-Zugang: | Volltext bestellen |
| Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
| container_end_page | 2009 |
|---|---|
| container_issue | |
| container_start_page | 2006 |
| container_title | |
| container_volume | |
| creator | Kyoungtae Lee Yeonam Yoon Nan Sun |
| description | This paper presents the design of a first-order close-loop VCO based ΔΣ ADC. Unlike other VCO based ADC, it does not contain operational amplifier which is power hungry and scaling unfriendly. Also, by using two VCOs referring to each other, it has an intrinsic DEM capability that improves SNDR degradation caused by mismatches in the feedback DAC. The design is low power and area efficient. A prototype is designed in the 0.13um CMOS technology with a power supply of 1.5V. The input signal bandwidth is 10MHz. In SPICE simulation, 70dB of SNDR is achieved while consuming only 5.6mW. |
| doi_str_mv | 10.1109/ISCAS.2013.6572264 |
| format | Conference Proceeding |
| fullrecord | <record><control><sourceid>ieee_6IE</sourceid><recordid>TN_cdi_ieee_primary_6572264</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>6572264</ieee_id><sourcerecordid>6572264</sourcerecordid><originalsourceid>FETCH-LOGICAL-i90t-d67add77c5348000047fb0f8d231e02fc09b7194643b577b4099dad98d3268bf3</originalsourceid><addsrcrecordid>eNpVkFtKw0AYhccbWGo3oC-zACf-c_0zj2lSbaG1YIs-lqQzqSO2SiYiug534H66Jiv2xacPzoGPwyHknEPCOdir0SzPZokALhOjUQijDkjPYsqVQanRcHNIOoLrlHEt9NG_Duwx6YBAzpQEcUp6MT4BwM5ruMAOmWeUw2T4yfoPl1QnZr0DguvT2W1xR7df22-aFTl9i2Gzovf5lFVl9I6GTetXTdm-NJG-h_bxN2jCJoYlLQaTM3JSl8_R9_bskvn1YJ4P2Xh6M8qzMQsWWuYMls4hLrVU6W4TKKwrqFMnJPcg6iXYCrlVRslKI1YKrHWls6mTwqRVLbvk4k8bvPeL1yasy-Zjsb9I_gBaZlIb</addsrcrecordid><sourcetype>Publisher</sourcetype><iscdi>true</iscdi><recordtype>conference_proceeding</recordtype></control><display><type>conference_proceeding</type><title>A 10MHz-BW, 5.6mW, 70dB SNDR ΔΣ ADC using VCO-based integrators with intrinsic DEM</title><source>IEEE Electronic Library (IEL) Conference Proceedings</source><creator>Kyoungtae Lee ; Yeonam Yoon ; Nan Sun</creator><creatorcontrib>Kyoungtae Lee ; Yeonam Yoon ; Nan Sun</creatorcontrib><description>This paper presents the design of a first-order close-loop VCO based ΔΣ ADC. Unlike other VCO based ADC, it does not contain operational amplifier which is power hungry and scaling unfriendly. Also, by using two VCOs referring to each other, it has an intrinsic DEM capability that improves SNDR degradation caused by mismatches in the feedback DAC. The design is low power and area efficient. A prototype is designed in the 0.13um CMOS technology with a power supply of 1.5V. The input signal bandwidth is 10MHz. In SPICE simulation, 70dB of SNDR is achieved while consuming only 5.6mW.</description><identifier>ISSN: 0271-4302</identifier><identifier>ISBN: 9781467357609</identifier><identifier>ISBN: 146735760X</identifier><identifier>EISSN: 2158-1525</identifier><identifier>EISBN: 9781467357616</identifier><identifier>EISBN: 1467357618</identifier><identifier>EISBN: 9781467357623</identifier><identifier>EISBN: 1467357626</identifier><identifier>DOI: 10.1109/ISCAS.2013.6572264</identifier><language>eng</language><publisher>IEEE</publisher><subject>Bandwidth ; CMOS integrated circuits ; CMOS technology ; Degradation ; Noise ; SPICE ; Voltage-controlled oscillators</subject><ispartof>2013 IEEE International Symposium on Circuits and Systems (ISCAS), 2013, p.2006-2009</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/6572264$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,776,780,785,786,2051,27904,54898</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/6572264$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Kyoungtae Lee</creatorcontrib><creatorcontrib>Yeonam Yoon</creatorcontrib><creatorcontrib>Nan Sun</creatorcontrib><title>A 10MHz-BW, 5.6mW, 70dB SNDR ΔΣ ADC using VCO-based integrators with intrinsic DEM</title><title>2013 IEEE International Symposium on Circuits and Systems (ISCAS)</title><addtitle>ISCAS</addtitle><description>This paper presents the design of a first-order close-loop VCO based ΔΣ ADC. Unlike other VCO based ADC, it does not contain operational amplifier which is power hungry and scaling unfriendly. Also, by using two VCOs referring to each other, it has an intrinsic DEM capability that improves SNDR degradation caused by mismatches in the feedback DAC. The design is low power and area efficient. A prototype is designed in the 0.13um CMOS technology with a power supply of 1.5V. The input signal bandwidth is 10MHz. In SPICE simulation, 70dB of SNDR is achieved while consuming only 5.6mW.</description><subject>Bandwidth</subject><subject>CMOS integrated circuits</subject><subject>CMOS technology</subject><subject>Degradation</subject><subject>Noise</subject><subject>SPICE</subject><subject>Voltage-controlled oscillators</subject><issn>0271-4302</issn><issn>2158-1525</issn><isbn>9781467357609</isbn><isbn>146735760X</isbn><isbn>9781467357616</isbn><isbn>1467357618</isbn><isbn>9781467357623</isbn><isbn>1467357626</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2013</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNpVkFtKw0AYhccbWGo3oC-zACf-c_0zj2lSbaG1YIs-lqQzqSO2SiYiug534H66Jiv2xacPzoGPwyHknEPCOdir0SzPZokALhOjUQijDkjPYsqVQanRcHNIOoLrlHEt9NG_Duwx6YBAzpQEcUp6MT4BwM5ruMAOmWeUw2T4yfoPl1QnZr0DguvT2W1xR7df22-aFTl9i2Gzovf5lFVl9I6GTetXTdm-NJG-h_bxN2jCJoYlLQaTM3JSl8_R9_bskvn1YJ4P2Xh6M8qzMQsWWuYMls4hLrVU6W4TKKwrqFMnJPcg6iXYCrlVRslKI1YKrHWls6mTwqRVLbvk4k8bvPeL1yasy-Zjsb9I_gBaZlIb</recordid><startdate>201305</startdate><enddate>201305</enddate><creator>Kyoungtae Lee</creator><creator>Yeonam Yoon</creator><creator>Nan Sun</creator><general>IEEE</general><scope>6IE</scope><scope>6IH</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIO</scope></search><sort><creationdate>201305</creationdate><title>A 10MHz-BW, 5.6mW, 70dB SNDR ΔΣ ADC using VCO-based integrators with intrinsic DEM</title><author>Kyoungtae Lee ; Yeonam Yoon ; Nan Sun</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i90t-d67add77c5348000047fb0f8d231e02fc09b7194643b577b4099dad98d3268bf3</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2013</creationdate><topic>Bandwidth</topic><topic>CMOS integrated circuits</topic><topic>CMOS technology</topic><topic>Degradation</topic><topic>Noise</topic><topic>SPICE</topic><topic>Voltage-controlled oscillators</topic><toplevel>online_resources</toplevel><creatorcontrib>Kyoungtae Lee</creatorcontrib><creatorcontrib>Yeonam Yoon</creatorcontrib><creatorcontrib>Nan Sun</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan (POP) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP) 1998-present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Kyoungtae Lee</au><au>Yeonam Yoon</au><au>Nan Sun</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>A 10MHz-BW, 5.6mW, 70dB SNDR ΔΣ ADC using VCO-based integrators with intrinsic DEM</atitle><btitle>2013 IEEE International Symposium on Circuits and Systems (ISCAS)</btitle><stitle>ISCAS</stitle><date>2013-05</date><risdate>2013</risdate><spage>2006</spage><epage>2009</epage><pages>2006-2009</pages><issn>0271-4302</issn><eissn>2158-1525</eissn><isbn>9781467357609</isbn><isbn>146735760X</isbn><eisbn>9781467357616</eisbn><eisbn>1467357618</eisbn><eisbn>9781467357623</eisbn><eisbn>1467357626</eisbn><abstract>This paper presents the design of a first-order close-loop VCO based ΔΣ ADC. Unlike other VCO based ADC, it does not contain operational amplifier which is power hungry and scaling unfriendly. Also, by using two VCOs referring to each other, it has an intrinsic DEM capability that improves SNDR degradation caused by mismatches in the feedback DAC. The design is low power and area efficient. A prototype is designed in the 0.13um CMOS technology with a power supply of 1.5V. The input signal bandwidth is 10MHz. In SPICE simulation, 70dB of SNDR is achieved while consuming only 5.6mW.</abstract><pub>IEEE</pub><doi>10.1109/ISCAS.2013.6572264</doi><tpages>4</tpages></addata></record> |
| fulltext | fulltext_linktorsrc |
| identifier | ISSN: 0271-4302 |
| ispartof | 2013 IEEE International Symposium on Circuits and Systems (ISCAS), 2013, p.2006-2009 |
| issn | 0271-4302 2158-1525 |
| language | eng |
| recordid | cdi_ieee_primary_6572264 |
| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Bandwidth CMOS integrated circuits CMOS technology Degradation Noise SPICE Voltage-controlled oscillators |
| title | A 10MHz-BW, 5.6mW, 70dB SNDR ΔΣ ADC using VCO-based integrators with intrinsic DEM |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-25T15%3A44%3A53IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-ieee_6IE&rft_val_fmt=info:ofi/fmt:kev:mtx:book&rft.genre=proceeding&rft.atitle=A%2010MHz-BW,%205.6mW,%2070dB%20SNDR%20%CE%94%CE%A3%20ADC%20using%20VCO-based%20integrators%20with%20intrinsic%20DEM&rft.btitle=2013%20IEEE%20International%20Symposium%20on%20Circuits%20and%20Systems%20(ISCAS)&rft.au=Kyoungtae%20Lee&rft.date=2013-05&rft.spage=2006&rft.epage=2009&rft.pages=2006-2009&rft.issn=0271-4302&rft.eissn=2158-1525&rft.isbn=9781467357609&rft.isbn_list=146735760X&rft_id=info:doi/10.1109/ISCAS.2013.6572264&rft_dat=%3Cieee_6IE%3E6572264%3C/ieee_6IE%3E%3Curl%3E%3C/url%3E&rft.eisbn=9781467357616&rft.eisbn_list=1467357618&rft.eisbn_list=9781467357623&rft.eisbn_list=1467357626&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rft_ieee_id=6572264&rfr_iscdi=true |