A 10MHz-BW, 5.6mW, 70dB SNDR ΔΣ ADC using VCO-based integrators with intrinsic DEM

This paper presents the design of a first-order close-loop VCO based ΔΣ ADC. Unlike other VCO based ADC, it does not contain operational amplifier which is power hungry and scaling unfriendly. Also, by using two VCOs referring to each other, it has an intrinsic DEM capability that improves SNDR degradation caused by mismatches in the feedback DAC. The design is low power and area efficient. A prototype is designed in the 0.13um CMOS technology with a power supply of 1.5V. The input signal bandwidth is 10MHz. In SPICE simulation, 70dB of SNDR is achieved while consuming only 5.6mW.