A 20Gb/s 136fJ/b 12.5Gb/s/μm on-chip link in 28nm CMOS
A high data rate, low power on-chip link in 28nm CMOS is presented. It features a double-sampling receiver with dynamic offset modulation and a capacitively-driven transmitter. The functionality of the link was validated using 4-7mm minimum-pitch on-chip wires. It achieves up to 20Gb/s of data rate...
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| creator | Nazari, Meisam Honarvar Emami-Neyestanak, Azita |
| description | A high data rate, low power on-chip link in 28nm CMOS is presented. It features a double-sampling receiver with dynamic offset modulation and a capacitively-driven transmitter. The functionality of the link was validated using 4-7mm minimum-pitch on-chip wires. It achieves up to 20Gb/s of data rate (13.9Gb/s/μm) with BER |
| doi_str_mv | 10.1109/RFIC.2013.6569576 |
| format | Conference Proceeding |
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It features a double-sampling receiver with dynamic offset modulation and a capacitively-driven transmitter. The functionality of the link was validated using 4-7mm minimum-pitch on-chip wires. It achieves up to 20Gb/s of data rate (13.9Gb/s/μm) with BER<; 10 -12 . It has better than 136fJ/b of power efficiency at 10Gb/s. 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It features a double-sampling receiver with dynamic offset modulation and a capacitively-driven transmitter. The functionality of the link was validated using 4-7mm minimum-pitch on-chip wires. It achieves up to 20Gb/s of data rate (13.9Gb/s/μm) with BER<; 10 -12 . It has better than 136fJ/b of power efficiency at 10Gb/s. The total area of the transmitter and receiver is 1110μm 2 .</description><subject>Bandwidth</subject><subject>Capacitors</subject><subject>Crosstalk</subject><subject>Double-sampling</subject><subject>Dynamic offset modulation</subject><subject>Interconnect</subject><subject>Modulation</subject><subject>On-chip signaling</subject><subject>Power demand</subject><subject>Receivers</subject><subject>System-on-chip</subject><subject>Wires</subject><issn>1529-2517</issn><issn>2375-0995</issn><isbn>9781467360593</isbn><isbn>1467360597</isbn><isbn>9781467360609</isbn><isbn>1467360627</isbn><isbn>9781467360623</isbn><isbn>1467360600</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2013</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNpNkEtOwzAURc1PIipZAGLiDTh5z5_neFhFtBQVVeIzrhzHFoY2VA0T9sYaWBMgOmB0pXOkM7iMXSJUiODq-9mirSSgqsiQM5aOWOlsg5qsIiBwx6yQyhoBzpmT_844dcoKNNIJadCes3IcXwDgJ0sOqWB2yiXMu3rkqCjd1h1HWZlfUH99bvnbIMJz3vFNHl55Hrhshi1v71YPF-ws-c0Yy8NO2NPs-rG9EcvVfNFOlyKjNe8iSUTtfWhs6mVvUg8-WKeV7mwKoJqOSJJTsbEaTU9BehMUxqRlb1MTkpqwq79ujjGud_u89fuP9eEG9Q0NdUfO</recordid><startdate>201306</startdate><enddate>201306</enddate><creator>Nazari, Meisam Honarvar</creator><creator>Emami-Neyestanak, Azita</creator><general>IEEE</general><scope>6IE</scope><scope>6IH</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIO</scope></search><sort><creationdate>201306</creationdate><title>A 20Gb/s 136fJ/b 12.5Gb/s/μm on-chip link in 28nm CMOS</title><author>Nazari, Meisam Honarvar ; Emami-Neyestanak, Azita</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i175t-f2114aac87fd2d5fd0ac79434b7fc038b662693e87415d6c2a5c31ef42d7f8cf3</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2013</creationdate><topic>Bandwidth</topic><topic>Capacitors</topic><topic>Crosstalk</topic><topic>Double-sampling</topic><topic>Dynamic offset modulation</topic><topic>Interconnect</topic><topic>Modulation</topic><topic>On-chip signaling</topic><topic>Power demand</topic><topic>Receivers</topic><topic>System-on-chip</topic><topic>Wires</topic><toplevel>online_resources</toplevel><creatorcontrib>Nazari, Meisam Honarvar</creatorcontrib><creatorcontrib>Emami-Neyestanak, Azita</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan (POP) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP) 1998-present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Nazari, Meisam Honarvar</au><au>Emami-Neyestanak, Azita</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>A 20Gb/s 136fJ/b 12.5Gb/s/μm on-chip link in 28nm CMOS</atitle><btitle>2013 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)</btitle><stitle>RFIC</stitle><date>2013-06</date><risdate>2013</risdate><spage>257</spage><epage>260</epage><pages>257-260</pages><issn>1529-2517</issn><eissn>2375-0995</eissn><isbn>9781467360593</isbn><isbn>1467360597</isbn><eisbn>9781467360609</eisbn><eisbn>1467360627</eisbn><eisbn>9781467360623</eisbn><eisbn>1467360600</eisbn><abstract>A high data rate, low power on-chip link in 28nm CMOS is presented. It features a double-sampling receiver with dynamic offset modulation and a capacitively-driven transmitter. The functionality of the link was validated using 4-7mm minimum-pitch on-chip wires. It achieves up to 20Gb/s of data rate (13.9Gb/s/μm) with BER<; 10 -12 . It has better than 136fJ/b of power efficiency at 10Gb/s. The total area of the transmitter and receiver is 1110μm 2 .</abstract><pub>IEEE</pub><doi>10.1109/RFIC.2013.6569576</doi><tpages>4</tpages></addata></record> |
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| identifier | ISSN: 1529-2517 |
| ispartof | 2013 IEEE Radio Frequency Integrated Circuits Symposium (RFIC), 2013, p.257-260 |
| issn | 1529-2517 2375-0995 |
| language | eng |
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| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Bandwidth Capacitors Crosstalk Double-sampling Dynamic offset modulation Interconnect Modulation On-chip signaling Power demand Receivers System-on-chip Wires |
| title | A 20Gb/s 136fJ/b 12.5Gb/s/μm on-chip link in 28nm CMOS |
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