A 20Gb/s 136fJ/b 12.5Gb/s/μm on-chip link in 28nm CMOS

A 20Gb/s 136fJ/b 12.5Gb/s/μm on-chip link in 28nm CMOS

A high data rate, low power on-chip link in 28nm CMOS is presented. It features a double-sampling receiver with dynamic offset modulation and a capacitively-driven transmitter. The functionality of the link was validated using 4-7mm minimum-pitch on-chip wires. It achieves up to 20Gb/s of data rate...

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Bibliographische Detailangaben
Hauptverfasser: Nazari, Meisam Honarvar, Emami-Neyestanak, Azita
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Bandwidth
Capacitors
Crosstalk
Double-sampling
Dynamic offset modulation
Interconnect
Modulation
On-chip signaling
Power demand
Receivers
System-on-chip
Wires
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Beschreibung
Zusammenfassung:A high data rate, low power on-chip link in 28nm CMOS is presented. It features a double-sampling receiver with dynamic offset modulation and a capacitively-driven transmitter. The functionality of the link was validated using 4-7mm minimum-pitch on-chip wires. It achieves up to 20Gb/s of data rate (13.9Gb/s/μm) with BER
ISSN:1529-2517
2375-0995
DOI:10.1109/RFIC.2013.6569576