Single-Cycle Multihop Asynchronous Repeated Traversal: A SMART Future for Reconfigurable On-Chip Networks

Future scalability for kilo-core architectures requires solutions beyond the capabilities of protocol and software design. Single-cycle multihop asynchronous repeated traversal (SMART) creates virtual single-cycle paths across the shared network between cores, potentially offering significant reduct...

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Veröffentlicht in:	Computer (Long Beach, Calif.) Calif.), 2013-10, Vol.46 (10), p.48-55
Hauptverfasser:	Krishna, Tushar, Chen, Chia-Hsin Owen, Sunghyun Park, Woo-Cheol Kwon, Subramanian, Suvinay, Chandrakasan, Anantha P., Li-Shiuan Peh
Format:	Artikel
Sprache:	eng
Schlagworte:	Asynchronous cache coherence traffic Computer architecture Computer programs Design methodology efficient network design Expenditures interconnection network Mathematical models multicore architecture Multicore processing Multiprocessing network-on-chip Networks NoC on-chip latency parallel computer architecture Ports (Computers) private L2 Radio mobile Reduction Run time (computers) Scalability scalable networks shared L2 SoC Software System-on-chip
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Beschreibung
Zusammenfassung:	Future scalability for kilo-core architectures requires solutions beyond the capabilities of protocol and software design. Single-cycle multihop asynchronous repeated traversal (SMART) creates virtual single-cycle paths across the shared network between cores, potentially offering significant reductions in runtime latency and energy expenditure.
ISSN:	0018-9162 1558-0814
DOI:	10.1109/MC.2013.260