An accurate and scalable analytic model for round-robin arbitration in network-on-chip

Due to continuously increasing performance requirements of embedded applications, today's multi-processor system-on-chips will evolve towards many-core system-on-chips with thousands of processors on a single chip. Accurate, fast and flexible (i.e., parameterizable) simulation models are necessary to be able to analyze and optimize these large systems. Network-on-chip is a common solution for the interconnection of large processor arrays. Existing analytic models for the performance analysis of network-on-chip often possess a lack of accuracy, if applied for the popular round-robin arbitration scheme. It turns out to be challenging to find an appropriate analytic representation for this apparently simple scheme. In this paper, we propose an accurate service time estimation model that is designed for round-robin arbiters. It is further employed to a queueing model for network-on-chip. The comparison with cycle-accurate simulation proves the accuracy of the proposed service time model, which is essential for predicting key performance indicators, such as network throughput or latencies.