Real-time FPGA implementation of efficient filter-banks for digitally sub-banded coherent DFT-S OFDM receiver

Real-time FPGA implementation of efficient filter-banks for digitally sub-banded coherent DFT-S OFDM receiver

We demonstrate a real-time FPGA realization of dual polarization filter banks - this high-speed 2×25 GBd low-complexity core establishes feasibility of energy-efficient (multipliers count ~halved) HW architecture for a digitally sub-banded 170 Gb/s DFT-S OFDM receiver.

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Bibliographische Detailangaben
Hauptverfasser: Tolmachev, A., Orbach, M., Meltsin, M., Hilgendorf, R., Birk, T., Nazarathy, M.
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Digital filters
Field programmable gate arrays
Filter banks
OFDM
Optical filters
Real-time systems
Receivers
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Beschreibung
Zusammenfassung:We demonstrate a real-time FPGA realization of dual polarization filter banks - this high-speed 2×25 GBd low-complexity core establishes feasibility of energy-efficient (multipliers count ~halved) HW architecture for a digitally sub-banded 170 Gb/s DFT-S OFDM receiver.
DOI:10.1364/OFC.2013.OW3B.1