Efficient multiplier-free FPGA demonstration of polar-domain multi-symbol-delay-detector (MSDD) for high performance phase recovery of 16-QAM
We eliminate all multipliers from the MSDD carrier recovery (CR) sub-system without performance penalty. The extreme-low-complexity CR is demonstrated in real-time in FPGA HW.
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| creator | Tolmachev, A. Tselniker, I. Meltsin, M. Sigron, I. Nazarathy, M. |
| description | We eliminate all multipliers from the MSDD carrier recovery (CR) sub-system without performance penalty. The extreme-low-complexity CR is demonstrated in real-time in FPGA HW. |
| doi_str_mv | 10.1364/OFC.2013.OM2C.8 |
| format | Conference Proceeding |
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| ispartof | 2013 Optical Fiber Communication Conference and Exposition and the National Fiber Optic Engineers Conference (OFC/NFOEC), 2013, p.1-3 |
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| language | eng |
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| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Complexity theory Field programmable gate arrays Hardware Optical noise Phase noise Real-time systems Signal to noise ratio |
| title | Efficient multiplier-free FPGA demonstration of polar-domain multi-symbol-delay-detector (MSDD) for high performance phase recovery of 16-QAM |
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