Efficient multiplier-free FPGA demonstration of polar-domain multi-symbol-delay-detector (MSDD) for high performance phase recovery of 16-QAM

Efficient multiplier-free FPGA demonstration of polar-domain multi-symbol-delay-detector (MSDD) for high performance phase recovery of 16-QAM

We eliminate all multipliers from the MSDD carrier recovery (CR) sub-system without performance penalty. The extreme-low-complexity CR is demonstrated in real-time in FPGA HW.

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Bibliographische Detailangaben
Hauptverfasser: Tolmachev, A., Tselniker, I., Meltsin, M., Sigron, I., Nazarathy, M.
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Complexity theory
Field programmable gate arrays
Hardware
Optical noise
Phase noise
Real-time systems
Signal to noise ratio
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Beschreibung
Zusammenfassung:We eliminate all multipliers from the MSDD carrier recovery (CR) sub-system without performance penalty. The extreme-low-complexity CR is demonstrated in real-time in FPGA HW.
DOI:10.1364/OFC.2013.OM2C.8