A Highly Integrable FPGA-Based Runtime-Configurable Multilayer Perceptron
In this paper, a highly integrable Field Programmable Gate Array-based hardware design of multilayer perceptron as a realization of an artificial neural network is presented. Such a hardware solution ensures a deterministic behavior required for any hard real-time compositions. The integration into...
Gespeichert in:
Hauptverfasser: | , , , , |
---|---|
Format: | Tagungsbericht |
Sprache: | eng |
Schlagworte: | |
Online-Zugang: | Volltext bestellen |
Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
Schreiben Sie den ersten Kommentar!