A Highly Integrable FPGA-Based Runtime-Configurable Multilayer Perceptron

In this paper, a highly integrable Field Programmable Gate Array-based hardware design of multilayer perceptron as a realization of an artificial neural network is presented. Such a hardware solution ensures a deterministic behavior required for any hard real-time compositions. The integration into existing systems is achieved by the application of UDP/IP. %A developed protocol enables the hardware solution to act as a stand-alone device with no need for an additional host PC. Additionally, the presented design is highly flexible due to a parameterizable multilayer perceptron approach. However, most reconfigurations usually require a hard coded reimplementation, resynthesis, and the download of a new bit file to the target platform, which also requires an additional host PC. Contrary with the presented solution, it is possible to configure the multilayer perceptron's parameters during runtime via a software interface. This approach allows the multilayer perceptron to be adapted to nearly any application. The developed design combines the flexibility of a software solution to generate and comfortably reconfigure the multilayer perceptron as well as the high performance of a hardware solution. %The investigation of hardware utilization and performance of a running prototype stützt%Finally, the hardware utilization and performance are investigated. As proof of concept, a running prototype has been realized, which shows the design to be highly flexible and with good performance while the hardware resource consumption is kept minimal.