Comparative study & analysis of 32nm FD-SOI/SON and CNFET based 4×4 SRAM Cell Array
As the CMOS technology is being scaled down, there has been a major thrust to improve the performance and robustness of the memory used in hand-held devices. Static Random Access Memory (SRAM) is the fundamental unit of Cache Memory. As the technology advances, a large percentage of the chip area is...
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| creator | Saha, Deepon Saha, Priyanka Naskar, Kousik Jain, Amit Sarkar, Subir Kumar |
| description | As the CMOS technology is being scaled down, there has been a major thrust to improve the performance and robustness of the memory used in hand-held devices. Static Random Access Memory (SRAM) is the fundamental unit of Cache Memory. As the technology advances, a large percentage of the chip area is taken up by on-chip cache. Power consumption is also an issue as large bit-line capacitances require charging/discharging during write/read operation. The future devices with advanced technology promises of low power application. In this paper, we have illustrated the implementation of a 6T SRAM array (4×4) using future devices in 32nm Technology. A comparative circuit level analysis between Silicon on Insulator (SOI), Silicon on Nothing (SON) and Carbon Nanotube Field Effect Transistor (CNFET) has been presented. Synopsys Hspice tool has been utilized for simulation purpose. |
| doi_str_mv | 10.1109/ICCPCT.2013.6528857 |
| format | Conference Proceeding |
| fullrecord | <record><control><sourceid>ieee_6IE</sourceid><recordid>TN_cdi_ieee_primary_6528857</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>6528857</ieee_id><sourcerecordid>6528857</sourcerecordid><originalsourceid>FETCH-LOGICAL-i90t-e4cfb95c629c15c612dc1d92cb936481d0626b91334caf3ba3827102642a7fff3</originalsourceid><addsrcrecordid>eNpVkMFKxDAYhCMiKGufYC85eWs3-ZOmzbFE1y2sW7G9L0mbQKDdXZoq9El8IF_Mgnvx9DEMMwyD0JqShFIiN6VS76pJgFCWiBTyPM1uUCSznHKRMS4B4Pafpuk9ikLwhoDIBKSCPaBGnYeLHvXkvywO02c34yesT7qfgw_47DCD04C3z3FdlZu6Oixeh9Vh-9Jgo4PtMP_55rj-KN6wsn2Pi3HU8yO6c7oPNrpyhZoloHbxvnotVbGPvSRTbHnrjExbAbKlCyh0Le0ktEYywXPaEQHCSMoYb7VjRrMcMrps56Az5xxbofVfrbfWHi-jH_Q4H69XsF_gAU9D</addsrcrecordid><sourcetype>Publisher</sourcetype><iscdi>true</iscdi><recordtype>conference_proceeding</recordtype></control><display><type>conference_proceeding</type><title>Comparative study & analysis of 32nm FD-SOI/SON and CNFET based 4×4 SRAM Cell Array</title><source>IEEE Electronic Library (IEL) Conference Proceedings</source><creator>Saha, Deepon ; Saha, Priyanka ; Naskar, Kousik ; Jain, Amit ; Sarkar, Subir Kumar</creator><creatorcontrib>Saha, Deepon ; Saha, Priyanka ; Naskar, Kousik ; Jain, Amit ; Sarkar, Subir Kumar</creatorcontrib><description>As the CMOS technology is being scaled down, there has been a major thrust to improve the performance and robustness of the memory used in hand-held devices. Static Random Access Memory (SRAM) is the fundamental unit of Cache Memory. As the technology advances, a large percentage of the chip area is taken up by on-chip cache. Power consumption is also an issue as large bit-line capacitances require charging/discharging during write/read operation. The future devices with advanced technology promises of low power application. In this paper, we have illustrated the implementation of a 6T SRAM array (4×4) using future devices in 32nm Technology. A comparative circuit level analysis between Silicon on Insulator (SOI), Silicon on Nothing (SON) and Carbon Nanotube Field Effect Transistor (CNFET) has been presented. Synopsys Hspice tool has been utilized for simulation purpose.</description><identifier>ISBN: 9781467349215</identifier><identifier>ISBN: 1467349216</identifier><identifier>EISBN: 9781467349222</identifier><identifier>EISBN: 9781467349208</identifier><identifier>EISBN: 1467349224</identifier><identifier>EISBN: 1467349208</identifier><identifier>DOI: 10.1109/ICCPCT.2013.6528857</identifier><language>eng</language><publisher>IEEE</publisher><subject>Carbon Nanotube Field Effect Transistor ; CNTFETs ; Lead ; Low Power ; MOSFET ; Nanoscale devices ; On-Chip Cache ; Random access memory ; Robustness ; Silicon on Insulator Technology ; Silicon on Nothing Technology ; SRAM Cell ; Substrates</subject><ispartof>2013 International Conference on Circuits, Power and Computing Technologies (ICCPCT), 2013, p.929-934</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/6528857$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,777,781,786,787,2052,27906,54901</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/6528857$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Saha, Deepon</creatorcontrib><creatorcontrib>Saha, Priyanka</creatorcontrib><creatorcontrib>Naskar, Kousik</creatorcontrib><creatorcontrib>Jain, Amit</creatorcontrib><creatorcontrib>Sarkar, Subir Kumar</creatorcontrib><title>Comparative study & analysis of 32nm FD-SOI/SON and CNFET based 4×4 SRAM Cell Array</title><title>2013 International Conference on Circuits, Power and Computing Technologies (ICCPCT)</title><addtitle>ICCPCT</addtitle><description>As the CMOS technology is being scaled down, there has been a major thrust to improve the performance and robustness of the memory used in hand-held devices. Static Random Access Memory (SRAM) is the fundamental unit of Cache Memory. As the technology advances, a large percentage of the chip area is taken up by on-chip cache. Power consumption is also an issue as large bit-line capacitances require charging/discharging during write/read operation. The future devices with advanced technology promises of low power application. In this paper, we have illustrated the implementation of a 6T SRAM array (4×4) using future devices in 32nm Technology. A comparative circuit level analysis between Silicon on Insulator (SOI), Silicon on Nothing (SON) and Carbon Nanotube Field Effect Transistor (CNFET) has been presented. Synopsys Hspice tool has been utilized for simulation purpose.</description><subject>Carbon Nanotube Field Effect Transistor</subject><subject>CNTFETs</subject><subject>Lead</subject><subject>Low Power</subject><subject>MOSFET</subject><subject>Nanoscale devices</subject><subject>On-Chip Cache</subject><subject>Random access memory</subject><subject>Robustness</subject><subject>Silicon on Insulator Technology</subject><subject>Silicon on Nothing Technology</subject><subject>SRAM Cell</subject><subject>Substrates</subject><isbn>9781467349215</isbn><isbn>1467349216</isbn><isbn>9781467349222</isbn><isbn>9781467349208</isbn><isbn>1467349224</isbn><isbn>1467349208</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2013</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNpVkMFKxDAYhCMiKGufYC85eWs3-ZOmzbFE1y2sW7G9L0mbQKDdXZoq9El8IF_Mgnvx9DEMMwyD0JqShFIiN6VS76pJgFCWiBTyPM1uUCSznHKRMS4B4Pafpuk9ikLwhoDIBKSCPaBGnYeLHvXkvywO02c34yesT7qfgw_47DCD04C3z3FdlZu6Oixeh9Vh-9Jgo4PtMP_55rj-KN6wsn2Pi3HU8yO6c7oPNrpyhZoloHbxvnotVbGPvSRTbHnrjExbAbKlCyh0Le0ktEYywXPaEQHCSMoYb7VjRrMcMrps56Az5xxbofVfrbfWHi-jH_Q4H69XsF_gAU9D</recordid><startdate>201303</startdate><enddate>201303</enddate><creator>Saha, Deepon</creator><creator>Saha, Priyanka</creator><creator>Naskar, Kousik</creator><creator>Jain, Amit</creator><creator>Sarkar, Subir Kumar</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>201303</creationdate><title>Comparative study & analysis of 32nm FD-SOI/SON and CNFET based 4×4 SRAM Cell Array</title><author>Saha, Deepon ; Saha, Priyanka ; Naskar, Kousik ; Jain, Amit ; Sarkar, Subir Kumar</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i90t-e4cfb95c629c15c612dc1d92cb936481d0626b91334caf3ba3827102642a7fff3</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2013</creationdate><topic>Carbon Nanotube Field Effect Transistor</topic><topic>CNTFETs</topic><topic>Lead</topic><topic>Low Power</topic><topic>MOSFET</topic><topic>Nanoscale devices</topic><topic>On-Chip Cache</topic><topic>Random access memory</topic><topic>Robustness</topic><topic>Silicon on Insulator Technology</topic><topic>Silicon on Nothing Technology</topic><topic>SRAM Cell</topic><topic>Substrates</topic><toplevel>online_resources</toplevel><creatorcontrib>Saha, Deepon</creatorcontrib><creatorcontrib>Saha, Priyanka</creatorcontrib><creatorcontrib>Naskar, Kousik</creatorcontrib><creatorcontrib>Jain, Amit</creatorcontrib><creatorcontrib>Sarkar, Subir Kumar</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Saha, Deepon</au><au>Saha, Priyanka</au><au>Naskar, Kousik</au><au>Jain, Amit</au><au>Sarkar, Subir Kumar</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Comparative study & analysis of 32nm FD-SOI/SON and CNFET based 4×4 SRAM Cell Array</atitle><btitle>2013 International Conference on Circuits, Power and Computing Technologies (ICCPCT)</btitle><stitle>ICCPCT</stitle><date>2013-03</date><risdate>2013</risdate><spage>929</spage><epage>934</epage><pages>929-934</pages><isbn>9781467349215</isbn><isbn>1467349216</isbn><eisbn>9781467349222</eisbn><eisbn>9781467349208</eisbn><eisbn>1467349224</eisbn><eisbn>1467349208</eisbn><abstract>As the CMOS technology is being scaled down, there has been a major thrust to improve the performance and robustness of the memory used in hand-held devices. Static Random Access Memory (SRAM) is the fundamental unit of Cache Memory. As the technology advances, a large percentage of the chip area is taken up by on-chip cache. Power consumption is also an issue as large bit-line capacitances require charging/discharging during write/read operation. The future devices with advanced technology promises of low power application. In this paper, we have illustrated the implementation of a 6T SRAM array (4×4) using future devices in 32nm Technology. A comparative circuit level analysis between Silicon on Insulator (SOI), Silicon on Nothing (SON) and Carbon Nanotube Field Effect Transistor (CNFET) has been presented. Synopsys Hspice tool has been utilized for simulation purpose.</abstract><pub>IEEE</pub><doi>10.1109/ICCPCT.2013.6528857</doi><tpages>6</tpages></addata></record> |
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| identifier | ISBN: 9781467349215 |
| ispartof | 2013 International Conference on Circuits, Power and Computing Technologies (ICCPCT), 2013, p.929-934 |
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| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Carbon Nanotube Field Effect Transistor CNTFETs Lead Low Power MOSFET Nanoscale devices On-Chip Cache Random access memory Robustness Silicon on Insulator Technology Silicon on Nothing Technology SRAM Cell Substrates |
| title | Comparative study & analysis of 32nm FD-SOI/SON and CNFET based 4×4 SRAM Cell Array |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-18T20%3A25%3A24IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-ieee_6IE&rft_val_fmt=info:ofi/fmt:kev:mtx:book&rft.genre=proceeding&rft.atitle=Comparative%20study%20&%20analysis%20of%2032nm%20FD-SOI/SON%20and%20CNFET%20based%204%C3%974%20SRAM%20Cell%20Array&rft.btitle=2013%20International%20Conference%20on%20Circuits,%20Power%20and%20Computing%20Technologies%20(ICCPCT)&rft.au=Saha,%20Deepon&rft.date=2013-03&rft.spage=929&rft.epage=934&rft.pages=929-934&rft.isbn=9781467349215&rft.isbn_list=1467349216&rft_id=info:doi/10.1109/ICCPCT.2013.6528857&rft_dat=%3Cieee_6IE%3E6528857%3C/ieee_6IE%3E%3Curl%3E%3C/url%3E&rft.eisbn=9781467349222&rft.eisbn_list=9781467349208&rft.eisbn_list=1467349224&rft.eisbn_list=1467349208&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rft_ieee_id=6528857&rfr_iscdi=true |