Comparative study & analysis of 32nm FD-SOI/SON and CNFET based 4×4 SRAM Cell Array

As the CMOS technology is being scaled down, there has been a major thrust to improve the performance and robustness of the memory used in hand-held devices. Static Random Access Memory (SRAM) is the fundamental unit of Cache Memory. As the technology advances, a large percentage of the chip area is taken up by on-chip cache. Power consumption is also an issue as large bit-line capacitances require charging/discharging during write/read operation. The future devices with advanced technology promises of low power application. In this paper, we have illustrated the implementation of a 6T SRAM array (4×4) using future devices in 32nm Technology. A comparative circuit level analysis between Silicon on Insulator (SOI), Silicon on Nothing (SON) and Carbon Nanotube Field Effect Transistor (CNFET) has been presented. Synopsys Hspice tool has been utilized for simulation purpose.