ESESC: A fast multicore simulator using Time-Based Sampling

Architects rely on simulation in their exploration of the design space. However, slow simulation speed caps their productivity and limits the depth of their exploration. Sampling has been a commonly used remedy. While sampling is shown to be an effective technique for single core processors, its app...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	Ardestani, E. K., Renau, J.
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Computational modeling Instruction sets Multicore processing Synchronization
Online-Zugang:	Volltext bestellen
Tags:	Tag hinzufügen Keine Tags, Fügen Sie den ersten Tag hinzu!