Transactional Memory Architecture and Implementation for IBM System Z

Transactional Memory Architecture and Implementation for IBM System Z

We present the introduction of transactional memory into the next generation IBM System z CPU. We first describe the instruction-set architecture features, including requirements for enterprise-class software RAS. We then describe the implementation in the IBM zEnterprise EC12 (zEC12) microprocessor...

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Bibliographische Detailangaben
Hauptverfasser: Jacobi, Christian, Slegel, Timothy, Greiner, Dan
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Hardware > Emerging technologies
Hardware > Hardware validation
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Beschreibung
Zusammenfassung:We present the introduction of transactional memory into the next generation IBM System z CPU. We first describe the instruction-set architecture features, including requirements for enterprise-class software RAS. We then describe the implementation in the IBM zEnterprise EC12 (zEC12) microprocessor generation, focusing on how transactional memory can be embedded into the existing cache design and multiprocessor shared-memory infrastructure. We explain practical reasons behind our choices. The zEC12 system is available since September 2012.
ISSN:1072-4451
DOI:10.1109/MICRO.2012.12