Comparative study on multistage amplifier and folded cascode amplifier design in sample and hold circuit using 0.18μm CMOS technology

This paper presents the comparison between multistage amplifier and folded cascode amplifier design using 0.18μm CMOS technology. The objective of this project is to compare gain and power dissipation between these two design models. Sample and hold circuit (SHC) is the main component in pipelined ADC. Designing a low power, high gain SHC is crucial, that is the main reason why multistage amplifier is applied in this project. Implementation has been done in 0.18μm technology, for a 5MHz sampling frequency, considering 1.2 Vpp voltage and 1.8V voltage supply using SILVACO EDA tools. From the simulation, the multistage amplifier consumes 0.139mW power and has gain of 94.64dB. The folded cascode amplifier has 6.5mW power dissipation and 70dB gain. From the simulation results, the multistage amplifier is better in term of gain and power dissipation than the folded cascode design.