A highly integrated 65-nm SoC process with enhanced power/performance of digital and analog circuits

65nm Deeply Depleted Channel (DDC TM ) transistors have been fabricated with a halo-free, un-doped epitaxial channel and enable reduced threshold voltage (V T ) variation, lower supply voltage (V CC ), enhanced body effect and I EFF . Digital circuits made using this technology show benefits ranging...

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Bibliographische Detailangaben
Hauptverfasser:	Clark, L. T., Zhao, D., Bakhishev, T., Ahn, H., Boling, E., Duane, M., Fujita, K., Gregory, P., Hoffmann, T., Hori, M., Kanai, D., Kidd, D., Lee, S., Liu, Y., Mitani, J., Nagayama, J., Pradhan, S., Ranade, P., Rogenmoser, R., Scudder, L., Shifren, L., Torii, Y., Wojko, M., Asada, Y., Ema, T., Thompson, S.
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Analog circuits Logic gates Mirrors MOS devices Process control Random access memory Transistors
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Beschreibung
Zusammenfassung:	65nm Deeply Depleted Channel (DDC TM ) transistors have been fabricated with a halo-free, un-doped epitaxial channel and enable reduced threshold voltage (V T ) variation, lower supply voltage (V CC ), enhanced body effect and I EFF . Digital circuits made using this technology show benefits ranging from 47% power reduction to 38% frequency increase. Analog circuits exhibit 4x greater amplifier gain despite lower V DD , and current mirror mismatch (both global and local) shows 40% and 30% reduction for NMOS and PMOS, respectively.
ISSN:	0163-1918 2156-017X
DOI:	10.1109/IEDM.2012.6479042