Scaling directions for 2D and 3D NAND cells

This paper describes NAND cell scaling directions for 20nm and beyond. Many of the 2D NAND cell scaling challenges can be resolved by a planar floating gate (FG) cell. Scaling directions and key technology requirements for 3D NAND are also discussed.

Gespeichert in:

Bibliographische Detailangaben
Hauptverfasser:	Goda, A., Parat, K.
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Computer architecture Conductivity Interference Logic gates Noise Reliability Very large scale integration
Online-Zugang:	Volltext bestellen
Tags:	Tag hinzufügen Keine Tags, Fügen Sie den ersten Tag hinzu!

Schreiben Sie den ersten Kommentar!