Scaling directions for 2D and 3D NAND cells

Scaling directions for 2D and 3D NAND cells

This paper describes NAND cell scaling directions for 20nm and beyond. Many of the 2D NAND cell scaling challenges can be resolved by a planar floating gate (FG) cell. Scaling directions and key technology requirements for 3D NAND are also discussed.

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Bibliographische Detailangaben
Hauptverfasser: Goda, A., Parat, K.
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Computer architecture
Conductivity
Interference
Logic gates
Noise
Reliability
Very large scale integration
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Beschreibung
Zusammenfassung:This paper describes NAND cell scaling directions for 20nm and beyond. Many of the 2D NAND cell scaling challenges can be resolved by a planar floating gate (FG) cell. Scaling directions and key technology requirements for 3D NAND are also discussed.
ISSN:0163-1918
2156-017X
DOI:10.1109/IEDM.2012.6478961