Gate Mapping Automation for Asynchronous NULL Convention Logic Circuits

Design automation techniques are a key challenge in the widespread application of timing-robust asynchronous circuit styles. In this paper, a new methodology for mapping multi-rail logic expressions to a NULL convention logic (NCL) gate library is proposed. The new methodology is then compared to an...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Veröffentlicht in:IEEE transactions on very large scale integration (VLSI) systems 2014-01, Vol.22 (1), p.99-112
Hauptverfasser: Parsan, Farhad A., Al-Assadi, Waleed K., Smith, Scott C.
Format: Artikel
Sprache:eng
Schlagworte:
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
Beschreibung
Zusammenfassung:Design automation techniques are a key challenge in the widespread application of timing-robust asynchronous circuit styles. In this paper, a new methodology for mapping multi-rail logic expressions to a NULL convention logic (NCL) gate library is proposed. The new methodology is then compared to another recently proposed mapping approach, demonstrating that the new methodology can further reduce the area and improve the delay of NCL circuits. Also, in contrast to the original approach, which only targets area reduction, the new methodology can target any arbitrary cost function or use any subset of the NCL gate library for mapping. In order to automate the new methodology and compare it with the original one, both methodologies were implemented in the Perl programming language and compared in terms of mapping performance and runtime. The results show that, depending on the test circuit, the new methodology can offer up to 10% improvement in area, and 39% improvement in delay.
ISSN:1063-8210
1557-9999
DOI:10.1109/TVLSI.2012.2231889