A SHA-less 10-bit 80-MS/s CMOS pipelined ADC

A SHA-less 10-bit 80-MS/s CMOS pipelined ADC

This paper describes a 10-bit, 80MS/s CMOS pipelined Analog to Digital converter(ADC) that is implemented in a standard 180 nm technology. The ADC removes the Sample-and-Hold amplifier (SHA) to save power dissipation and die chip area. A 1.5 bit/stage architecture is used in the first stage to lower...

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Bibliographische Detailangaben
Hauptverfasser: Young-Mok Jung, Jin Zhe, Chan-Keun Kwon, Hoon-Ki Kim, Soo-Won Kim
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Clocks
CMOS integrated circuits
CMOS technology
Gain
Pipelines
Power dissipation
Switches
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Beschreibung
Zusammenfassung:This paper describes a 10-bit, 80MS/s CMOS pipelined Analog to Digital converter(ADC) that is implemented in a standard 180 nm technology. The ADC removes the Sample-and-Hold amplifier (SHA) to save power dissipation and die chip area. A 1.5 bit/stage architecture is used in the first stage to lower front-end. The pipelined ADC achieved a peak signal-to-noise-and-distortion ratio(SNR) of 58.2 dB, and a power consumption of 55 mW.
DOI:10.1109/ICSICT.2012.6467927