Estimating the starting point of conduction in nanoscale CMOS gates

In this paper a method for calculating the starting point of conduction of parallel and serial transistor structures in CMOS gates for the nanoscale regime is introduced. The calculation of the starting point is necessary for modeling the operation of complex gates. The influence of the parasitic capacitances is determined and the subthreshold and conducting behavior of the transistors are considered for the analysis of the operation of the serial transistor structure. Appropriate assumptions are used for modeling the circuit operation whose efficiency is determined by the accuracy of the results compared to HSPICE simulations. The overall accuracy of the proposed method is verified through HSPICE simulations for 32nm high k dielectric PTM technology.