Efficient implementation scheme of a real-time radar beamformer on a VLIW DSP processor, TMS320C66x TI DSP implementation

Beamforming has been known to be mostly implemented on FPGAs and ASICs due to high real-time constraints on computation capability and bandwidth limits. However, recent advances in digital signal processors (DSP) showed great performance improvements with very low power consumption, making it promising to perform a phased array beamforming in flexible software instead of analog or hardware solutions. VLIW DSP processors are powered by an instruction level parallelism (ILP), offering the possibility to execute multiple separate instructions in one clock cycle. Even so, there is a big challenge on associated compilers which cannot guarantee the best use of resources, and then decrease obtained performance. We describe in this paper an efficient assembly implementation scheme for the beamforming algorithm, which exploits at best the available hardware units so as to minimize the execution time. Our experimental results on the high-end TMS320C6678 VLIW TI DSP, reached an average gain of 77.5% for the number of needed clock cycles relatively to conventional compiled implementations.