Three stage low noise operational amplifier design for a 0.18 um CMOS process

Three stage low noise operational amplifier design for a 0.18 um CMOS process

A new three stage low-noise, high-gain operational amplifier (Op-Amp) is proposed in this paper. Design strategies are discussed for minimizing noise and increasing gain. Multipath nested Miller compensation used for three stage operational amplifier. The circuit is designed in the 0.18μm CMOS techn...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: Soltani, A., Yaghmaie, M., Razeghi, B., Pourandoost, R., Tous, S. I., Golmakani, A.
Format: Tagungsbericht
Sprache:eng
Schlagworte:
1f noise
CMOS integrated circuits
Flicker noise
Gain
Logic gates
Nested Miller compensation
Noise
Operational amplifiers
Thermal noise
three stage operational Amplifier
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
Beschreibung
Zusammenfassung:A new three stage low-noise, high-gain operational amplifier (Op-Amp) is proposed in this paper. Design strategies are discussed for minimizing noise and increasing gain. Multipath nested Miller compensation used for three stage operational amplifier. The circuit is designed in the 0.18μm CMOS technology. The HSPICE software was used for simulation. The simulation results show that the amplifier has a 128.5 dB open-loop DC gain and a unity gain-bandwidth of 794 MHz. Also input-referred noise of this circuit is 1.233 (nF/√(Hz)) at 1 MHz frequency.
DOI:10.1109/ICEEE.2012.6421117