Thermal management of packages with 3D die stacking

The objective of thermal design requirement for 3D stacked die package is to maintain the junction temperatures of active devices in the package at or below specified limits. In this paper, die-to-die thermal resistance is identified as the key bottleneck in 3D thermal management, and two solution paths are proposed: fully-populated thermal bump array and thermally conductive underfill materials. The sensitivity of the thermal bump array design and the effective thermal conductivity of underfill materials will be discussed. In addition to die-to-die thermal resistance reduction, enhancement of the overall packaging cooling capability by integrating liquid cooling to the package heat spreader is another option especially for the server type of environment which typically dissipates high power. An alternative approach is to integrate thermo-electric cooling to the heat spreader for hot spot cooling. For systems that are limited to traditional air cooling, this paper will propose a different package architecture which will utilize existing cooling capability of 3D die stacking. Although the power dissipation capability of 3D die stacking is worse than the 2D multiple-chip packages, dual-die stacking can potentially achieve a higher efficiency of "performance per power" by utilizing the same concept of dual-core microprocessor. This approach is very useful especially when the package real estate is limited and 3D die stacking is the preferred package architecture.