Effective and efficient layer assignment for minimizing the temperature rise of large three-dimensional circuits

Three-dimensional integrated circuit (3D IC) technology can improve the circuit performance and reduce the power dissipation. However, the heat generated by the stacked layers may cause a large amount of temperature rise. It is known that the layer assignment result has a great impact on the amount of temperature rise. Although the integer linear programming (ILP) approach can guarantee finding the minimum-temperature-rise layer assignment solution, solving the ILP formulation is an NP-hard problem. In this paper, we propose a heuristic algorithm to derive a near-optimal layer assignment solution in polynomial time complexity. Experimental results consistently show that our approach is very effective and efficient.