Design and implementation of dynamic Word-Line pulse write margin monitor for SRAM

Design and implementation of dynamic Word-Line pulse write margin monitor for SRAM

We present an all-digital monitor structure to measure the Write Margin (WM) with dynamic Word-Line (WL) pulse for standard CMOS 6T SRAM. Ring oscillator and frequency divider based structures are used to generate wide range WL pulses (150ps ~ 32ns) with resolution of 50ps. The bit-line voltage is t...

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Hauptverfasser: Shao-Cheng Wang, Geng-Cing Lin, Yi-Wei Lin, Ming-Chien Tsai, Yi-Wei Chiu, Shyh-Jye Jou, Ching-Te Chuang, Nan-Chun Lien, Wei-Chiang Shih, Kuen-Di Lee, Jyun-Kai Chu
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Delay
Frequency conversion
Frequency measurement
Logic gates
Pulse measurements
Random access memory
Ring oscillators
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Zusammenfassung:We present an all-digital monitor structure to measure the Write Margin (WM) with dynamic Word-Line (WL) pulse for standard CMOS 6T SRAM. Ring oscillator and frequency divider based structures are used to generate wide range WL pulses (150ps ~ 32ns) with resolution of 50ps. The bit-line voltage is then successively stepped down for dynamic Write Margin characterization under given word-line pulse width. An improved Skitter based structure is employed to measure the WL pulse width with resolution of 10 ~ 20ps. Implementation of a 256Kb test chip in UMC 55nm Standard Performance (SP) CMOS technology is described.
DOI:10.1109/APCCAS.2012.6418985