A combinatorial distributed architecture for Exascale computing

Computer architectures are expected to change to support Exascale computing in the near future. As energy and cooling constraints limit increases in microprocessor clock speeds and number of cores, computer companies are turning to parallel programming. Nowadays, parallel programming is achieved by increasing the number of processing elements in processor cores, increasing the number of processor cores itself and complicated parallel programming where programmer has the responsibility of allocating memory and synchronizing the communication between the processing elements as well as processor cores. It becomes increasingly difficult and expensive to design and produce shared memory machines with ever increasing number of processors. Increase in the number of processors is a major disadvantage when it comes to energy consumption. In this work, we present a new architecture for processor design based on pairwise balanced combinatorial interconnection of processing and memory elements. The proposed processor uses two operand instructions, so that the set of executable machine instructions is partitioned by these pairs. This kind of partition allows parallel processing of data-independent instructions. Since this partition is done at the compile time, the architecture extracts the instruction level parallelism without run-time overheads. We analyze and confirm the performance improvements through simulations. The suggested combinatorial arrangement gives set of architectures with various degrees of performance enhancement.