Centip3De: A 64-Core, 3D Stacked Near-Threshold System

Centip3De uses the synergy between 3D integration and near-threshold computing to create a reconfigurable system that provides both energy-efficient operation and techniques to address single-thread performance bottlenecks. The original Centip3De design is a seven-layer 3D stacked design with 128 co...

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Veröffentlicht in:	IEEE MICRO 2013-03, Vol.33 (2), p.8-16
Hauptverfasser:	Dreslinski, R. G., Fick, D., Giridhar, B., Gyouho Kim, Sangwon Seo, Fojtik, M., Satpathy, S., Yoonmyung Lee, Daeyeon Kim, Liu, N., Wieckowski, M., Chen, G., Sylvester, D., Blaauw, D., Mudge, T.
Format:	Artikel
Sprache:	eng
Schlagworte:	advanced technologies Bottlenecks Centip3De Computation Computers Design engineering Dynamic random access memory hardware Integrated circuit interconnections Integrated circuits Low power electronics low-power design power management Power system management Random access memory Reconfigurable control systems Silicon Three dimensional Three dimensional displays Threshold voltage Through-silicon vias types and design styles
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Beschreibung
Zusammenfassung:	Centip3De uses the synergy between 3D integration and near-threshold computing to create a reconfigurable system that provides both energy-efficient operation and techniques to address single-thread performance bottlenecks. The original Centip3De design is a seven-layer 3D stacked design with 128 cores and 256 Mbytes of DRAM. Silicon results show a two-layer, 64-core system in 130-nm technology, which achieved an energy efficiency of 3,930 DMIPS/W.
ISSN:	0272-1732 1937-4143
DOI:	10.1109/MM.2013.4