Integration of dual channel timing formatter system for high speed memory test equipment
This paper proposes a dual channel timing formatter system for high speed memory test equipment. The proposed architecture supports 256 kinds of waveform with 20ps timing resolution. Moreover, timing problem is reduced because a timing generator is embedded.
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| creator | Jaeseok Park Ingeol Lee Young-Seok Park Sung-Geun Kim Kyung Ho Ryu Dong-Hoon Jung Kangwook Jo Choong Keun Lee Hongil Yoon Seong-Ook Jung Woo-Young Choi Sungho Kang |
| description | This paper proposes a dual channel timing formatter system for high speed memory test equipment. The proposed architecture supports 256 kinds of waveform with 20ps timing resolution. Moreover, timing problem is reduced because a timing generator is embedded. |
| doi_str_mv | 10.1109/ISOCC.2012.6407070 |
| format | Conference Proceeding |
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The proposed architecture supports 256 kinds of waveform with 20ps timing resolution. Moreover, timing problem is reduced because a timing generator is embedded.</abstract><pub>IEEE</pub><doi>10.1109/ISOCC.2012.6407070</doi><tpages>3</tpages></addata></record> |
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| identifier | ISBN: 1467329894 |
| ispartof | 2012 International SoC Design Conference (ISOCC), 2012, p.185-187 |
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| language | eng |
| recordid | cdi_ieee_primary_6407070 |
| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | ATE Calibration Clocks Delay Generators Image edge detection memory test Test equipment timing formatter |
| title | Integration of dual channel timing formatter system for high speed memory test equipment |
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