Integration of dual channel timing formatter system for high speed memory test equipment

Integration of dual channel timing formatter system for high speed memory test equipment

This paper proposes a dual channel timing formatter system for high speed memory test equipment. The proposed architecture supports 256 kinds of waveform with 20ps timing resolution. Moreover, timing problem is reduced because a timing generator is embedded.

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Bibliographische Detailangaben
Hauptverfasser: Jaeseok Park, Ingeol Lee, Young-Seok Park, Sung-Geun Kim, Kyung Ho Ryu, Dong-Hoon Jung, Kangwook Jo, Choong Keun Lee, Hongil Yoon, Seong-Ook Jung, Woo-Young Choi, Sungho Kang
Format: Tagungsbericht
Sprache:eng
Schlagworte:
ATE
Calibration
Clocks
Delay
Generators
Image edge detection
memory test
Test equipment
timing formatter
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Beschreibung
Zusammenfassung:This paper proposes a dual channel timing formatter system for high speed memory test equipment. The proposed architecture supports 256 kinds of waveform with 20ps timing resolution. Moreover, timing problem is reduced because a timing generator is embedded.
DOI:10.1109/ISOCC.2012.6407070