A 1.1-V 12-bit 20-MS/s pipelined ADC with 1.8-Vpp full-swing in 0.13-μm CMOS
A front-end unity-gain 1-bit flip-around DAC (FADAC) is exploited in a 12-bit opamp-sharing pipelined ADC, allowing a 1.8-V pp full-swing input at a 1.1-V supply. The high input swing, coupled with a large feedback factor (≈1) of the FADAC, enables a low-voltage low-power design for a high resolutio...
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| creator | Peiyuan Wan Wei Lang Rui Jin Chi Zhang Pingfen Lin |
| description | A front-end unity-gain 1-bit flip-around DAC (FADAC) is exploited in a 12-bit opamp-sharing pipelined ADC, allowing a 1.8-V pp full-swing input at a 1.1-V supply. The high input swing, coupled with a large feedback factor (≈1) of the FADAC, enables a low-voltage low-power design for a high resolution pipelined ADC. The prototype 12-bit ADC operating at 20-MS/s and 1.1-V supply achieves a 66.4 dB SNDR and 76.7 dB SFDR with a 3 MHz input. The ADC consumes 5.2 mW of power and occupies an active area of 0.44 mm 2 in 0.13-μm CMOS. |
| doi_str_mv | 10.1109/RFIT.2012.6401620 |
| format | Conference Proceeding |
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The ADC consumes 5.2 mW of power and occupies an active area of 0.44 mm 2 in 0.13-μm CMOS.</description><subject>Calibration</subject><subject>Capacitors</subject><subject>CMOS integrated circuits</subject><subject>CMOS technology</subject><subject>Flip-around digital-to-analog converter (FADAC)</subject><subject>Gain</subject><subject>low-power</subject><subject>low-voltage</subject><subject>opamp-sharing</subject><subject>pipelined analog-to-digital converter (ADC)</subject><subject>Power demand</subject><subject>Prototypes</subject><isbn>9781467323031</isbn><isbn>1467323039</isbn><isbn>1467323047</isbn><isbn>9781467323055</isbn><isbn>1467323055</isbn><isbn>9781467323048</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2012</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNo1kN1Kw0AUhFdEUGseQLzZF9j0nLPb3exliFYLDQUbelvys6sraQhNpPhuPoPPZMB6NQzMDB_D2D1CjAh2_rpcFTEBUqwVoCa4YLeotJEkQZlLFlmT_HuJ1ywahg8AmLraEtywPOUYo9hxJFGFkROIfDsfeB9614bONTx9zPgpjO9TLhG7vuf-s23FcArdGw8dnzik-Pk-8CzfbO_YlS_bwUVnnbFi-VRkL2K9eV5l6VoEC6OQUi6sqWnCKKnUtfEVWrlwxjtyhhJQVWU8GFXaBD3oBpSu64SwRuVco-SMPfzNBufcvj-GQ3n82p8PkL8D2kkW</recordid><startdate>201211</startdate><enddate>201211</enddate><creator>Peiyuan Wan</creator><creator>Wei Lang</creator><creator>Rui Jin</creator><creator>Chi Zhang</creator><creator>Pingfen Lin</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>201211</creationdate><title>A 1.1-V 12-bit 20-MS/s pipelined ADC with 1.8-Vpp full-swing in 0.13-μm CMOS</title><author>Peiyuan Wan ; Wei Lang ; Rui Jin ; Chi Zhang ; Pingfen Lin</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i90t-333597c2001a2a6c7fb1935e7fe2e72804bb7f074a981f06d046cc821c14eed43</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2012</creationdate><topic>Calibration</topic><topic>Capacitors</topic><topic>CMOS integrated circuits</topic><topic>CMOS technology</topic><topic>Flip-around digital-to-analog converter (FADAC)</topic><topic>Gain</topic><topic>low-power</topic><topic>low-voltage</topic><topic>opamp-sharing</topic><topic>pipelined analog-to-digital converter (ADC)</topic><topic>Power demand</topic><topic>Prototypes</topic><toplevel>online_resources</toplevel><creatorcontrib>Peiyuan Wan</creatorcontrib><creatorcontrib>Wei Lang</creatorcontrib><creatorcontrib>Rui Jin</creatorcontrib><creatorcontrib>Chi Zhang</creatorcontrib><creatorcontrib>Pingfen Lin</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Peiyuan Wan</au><au>Wei Lang</au><au>Rui Jin</au><au>Chi Zhang</au><au>Pingfen Lin</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>A 1.1-V 12-bit 20-MS/s pipelined ADC with 1.8-Vpp full-swing in 0.13-μm CMOS</atitle><btitle>2012 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT)</btitle><stitle>RFIT</stitle><date>2012-11</date><risdate>2012</risdate><spage>80</spage><epage>82</epage><pages>80-82</pages><isbn>9781467323031</isbn><isbn>1467323039</isbn><eisbn>1467323047</eisbn><eisbn>9781467323055</eisbn><eisbn>1467323055</eisbn><eisbn>9781467323048</eisbn><abstract>A front-end unity-gain 1-bit flip-around DAC (FADAC) is exploited in a 12-bit opamp-sharing pipelined ADC, allowing a 1.8-V pp full-swing input at a 1.1-V supply. The high input swing, coupled with a large feedback factor (≈1) of the FADAC, enables a low-voltage low-power design for a high resolution pipelined ADC. The prototype 12-bit ADC operating at 20-MS/s and 1.1-V supply achieves a 66.4 dB SNDR and 76.7 dB SFDR with a 3 MHz input. The ADC consumes 5.2 mW of power and occupies an active area of 0.44 mm 2 in 0.13-μm CMOS.</abstract><pub>IEEE</pub><doi>10.1109/RFIT.2012.6401620</doi><tpages>3</tpages></addata></record> |
| fulltext | fulltext_linktorsrc |
| identifier | ISBN: 9781467323031 |
| ispartof | 2012 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT), 2012, p.80-82 |
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| language | eng |
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| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Calibration Capacitors CMOS integrated circuits CMOS technology Flip-around digital-to-analog converter (FADAC) Gain low-power low-voltage opamp-sharing pipelined analog-to-digital converter (ADC) Power demand Prototypes |
| title | A 1.1-V 12-bit 20-MS/s pipelined ADC with 1.8-Vpp full-swing in 0.13-μm CMOS |
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