A 1.1-V 12-bit 20-MS/s pipelined ADC with 1.8-Vpp full-swing in 0.13-μm CMOS

A 1.1-V 12-bit 20-MS/s pipelined ADC with 1.8-Vpp full-swing in 0.13-μm CMOS

A front-end unity-gain 1-bit flip-around DAC (FADAC) is exploited in a 12-bit opamp-sharing pipelined ADC, allowing a 1.8-V pp full-swing input at a 1.1-V supply. The high input swing, coupled with a large feedback factor (≈1) of the FADAC, enables a low-voltage low-power design for a high resolutio...

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Bibliographische Detailangaben
Hauptverfasser: Peiyuan Wan, Wei Lang, Rui Jin, Chi Zhang, Pingfen Lin
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Calibration
Capacitors
CMOS integrated circuits
CMOS technology
Flip-around digital-to-analog converter (FADAC)
Gain
low-power
low-voltage
opamp-sharing
pipelined analog-to-digital converter (ADC)
Power demand
Prototypes
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Beschreibung
Zusammenfassung:A front-end unity-gain 1-bit flip-around DAC (FADAC) is exploited in a 12-bit opamp-sharing pipelined ADC, allowing a 1.8-V pp full-swing input at a 1.1-V supply. The high input swing, coupled with a large feedback factor (≈1) of the FADAC, enables a low-voltage low-power design for a high resolution pipelined ADC. The prototype 12-bit ADC operating at 20-MS/s and 1.1-V supply achieves a 66.4 dB SNDR and 76.7 dB SFDR with a 3 MHz input. The ADC consumes 5.2 mW of power and occupies an active area of 0.44 mm 2 in 0.13-μm CMOS.
DOI:10.1109/RFIT.2012.6401620