A 1.7GS/s 6-bit Flash A/D converter with distributed offset cancelling sample-and-hold

A High-Speed Analog-to-Digital Converter was implemented utilizing a novel distributed sample-and-hold, output offset storage comparator. The number of storage capacitors is minimized by use of one offset cancellation stage per two amplifiers, a technique used for the first time, in our knowledge.

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Bibliographische Detailangaben
Hauptverfasser: Mountrichas, L., Laopoulos, T., Siskos, S.
Format: Tagungsbericht
Sprache:eng
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Beschreibung
Zusammenfassung:A High-Speed Analog-to-Digital Converter was implemented utilizing a novel distributed sample-and-hold, output offset storage comparator. The number of storage capacitors is minimized by use of one offset cancellation stage per two amplifiers, a technique used for the first time, in our knowledge.
ISSN:2164-1676
2164-1706
DOI:10.1109/SOCC.2012.6398379