High Speed Dynamic Partial Reconfiguration for Real Time Multimedia Signal Processing

The use of Field Programmable Gate Array (FPGA) based System on Chip (SoC) is a promising approach in Multimedia applications. In SoC, computationally intensive tasks are off-loaded to the hardware logic. A feature introduced with new FPGA devices, Dynamic Partial Reconfiguration (DPR) is suitable to change this hardware logic when needed and while the rest of the system continues its functioning. As the applications running on hardware logic are real-time and computationally intensive, in order to make use of DPR to change the hardware logic, the efficiency of the DPR process is crucial. This paper describes how a FPGA-based Multimedia Application (Audio-Video filtering), benefits from dynamic partial reconfiguration and a custom DPR controller: the Speed Efficient Dynamic Partial Reconfiguration Controller (SEDPRC). Experimental results have shown that the novel controller brings benefits to the reconfiguration time. Enhancements in reconfiguration throughput up to a 55× factor are achieved.