Software in silicon: the methodology behind Sun's GX graphics accelerator architecture
The Sun GX graphics engine uses the host CPU as the main controller and has all its graphics functionality hardwired directly into two large ASICs; the FBC (frame buffer controller) and TEC (transformation engine and cursor). The GX has only three instructions: rendering arbitrary, filled quadrilate...
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description | The Sun GX graphics engine uses the host CPU as the main controller and has all its graphics functionality hardwired directly into two large ASICs; the FBC (frame buffer controller) and TEC (transformation engine and cursor). The GX has only three instructions: rendering arbitrary, filled quadrilaterals; displaying precomputed pixel images; and block image transfers. With these instructions the GX can do at least 80% of the most used functions in its targeted markets: window systems, 2-D geometry, and 3-D wireframe. The criteria, limitations, and approaches used for the GX architecture design are described. The GX architecture, the technology used in its implementation, the functionality and performance needed by applications, and future enhancements to the GX family of graphics devices are presented.< > |
doi_str_mv | 10.1109/CMPCON.1990.63673 |
format | Conference Proceeding |
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The GX has only three instructions: rendering arbitrary, filled quadrilaterals; displaying precomputed pixel images; and block image transfers. With these instructions the GX can do at least 80% of the most used functions in its targeted markets: window systems, 2-D geometry, and 3-D wireframe. The criteria, limitations, and approaches used for the GX architecture design are described. The GX architecture, the technology used in its implementation, the functionality and performance needed by applications, and future enhancements to the GX family of graphics devices are presented.< ></description><identifier>ISBN: 9780818620287</identifier><identifier>ISBN: 0818620285</identifier><identifier>DOI: 10.1109/CMPCON.1990.63673</identifier><language>eng</language><publisher>IEEE Comput. Soc</publisher><subject>Acceleration ; Accelerator architectures ; Engines ; Graphics ; Hardware ; Power supplies ; Rendering (computer graphics) ; Silicon ; Sun ; Workstations</subject><ispartof>Digest of Papers Compcon Spring '90. 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Thirty-Fifth IEEE Computer Society International Conference on Intellectual Leverage</title><addtitle>CMPCON</addtitle><description>The Sun GX graphics engine uses the host CPU as the main controller and has all its graphics functionality hardwired directly into two large ASICs; the FBC (frame buffer controller) and TEC (transformation engine and cursor). The GX has only three instructions: rendering arbitrary, filled quadrilaterals; displaying precomputed pixel images; and block image transfers. With these instructions the GX can do at least 80% of the most used functions in its targeted markets: window systems, 2-D geometry, and 3-D wireframe. The criteria, limitations, and approaches used for the GX architecture design are described. The GX architecture, the technology used in its implementation, the functionality and performance needed by applications, and future enhancements to the GX family of graphics devices are presented.< ></description><subject>Acceleration</subject><subject>Accelerator architectures</subject><subject>Engines</subject><subject>Graphics</subject><subject>Hardware</subject><subject>Power supplies</subject><subject>Rendering (computer graphics)</subject><subject>Silicon</subject><subject>Sun</subject><subject>Workstations</subject><isbn>9780818620287</isbn><isbn>0818620285</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>1990</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNotj0tLAzEYRQMiKHV-QHfZuZoxj-blTgatQrVCi7grmcyXTmQ6U5IU6b93UO_mcjaXcxGaU1JRSsxd_fper98qagypJJeKX6DCKE001ZIRptUVKlL6IlMEU0zIa_SxGX3-thFwGHAKfXDjcI9zB_gAuRvbsR_3Z9xAF4YWb07DbcLLT7yP9tgFl7B1DnqINo8R2-i6kMHlU4QbdOltn6D47xnaPj1u6-dytV6-1A-rMmiZS9HKVtmGA2OLBeXSWW8Z8RN5AEGMEZyoxmgjaKOoco3xxEzitBWsZbzhMzT_mw0AsDvGcLDxvPu9zn8AekRPiA</recordid><startdate>1990</startdate><enddate>1990</enddate><creator>Priem, C.R.</creator><general>IEEE Comput. Soc</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>1990</creationdate><title>Software in silicon: the methodology behind Sun's GX graphics accelerator architecture</title><author>Priem, C.R.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i86t-5d6d7ab3e2244136cafa20f224fee50995307b98951b717cb9f092721d52d23b3</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>1990</creationdate><topic>Acceleration</topic><topic>Accelerator architectures</topic><topic>Engines</topic><topic>Graphics</topic><topic>Hardware</topic><topic>Power supplies</topic><topic>Rendering (computer graphics)</topic><topic>Silicon</topic><topic>Sun</topic><topic>Workstations</topic><toplevel>online_resources</toplevel><creatorcontrib>Priem, C.R.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Priem, C.R.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Software in silicon: the methodology behind Sun's GX graphics accelerator architecture</atitle><btitle>Digest of Papers Compcon Spring '90. Thirty-Fifth IEEE Computer Society International Conference on Intellectual Leverage</btitle><stitle>CMPCON</stitle><date>1990</date><risdate>1990</risdate><spage>195</spage><epage>197</epage><pages>195-197</pages><isbn>9780818620287</isbn><isbn>0818620285</isbn><abstract>The Sun GX graphics engine uses the host CPU as the main controller and has all its graphics functionality hardwired directly into two large ASICs; the FBC (frame buffer controller) and TEC (transformation engine and cursor). The GX has only three instructions: rendering arbitrary, filled quadrilaterals; displaying precomputed pixel images; and block image transfers. With these instructions the GX can do at least 80% of the most used functions in its targeted markets: window systems, 2-D geometry, and 3-D wireframe. The criteria, limitations, and approaches used for the GX architecture design are described. The GX architecture, the technology used in its implementation, the functionality and performance needed by applications, and future enhancements to the GX family of graphics devices are presented.< ></abstract><pub>IEEE Comput. Soc</pub><doi>10.1109/CMPCON.1990.63673</doi><tpages>3</tpages></addata></record> |
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identifier | ISBN: 9780818620287 |
ispartof | Digest of Papers Compcon Spring '90. Thirty-Fifth IEEE Computer Society International Conference on Intellectual Leverage, 1990, p.195-197 |
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language | eng |
recordid | cdi_ieee_primary_63673 |
source | IEEE Electronic Library (IEL) Conference Proceedings |
subjects | Acceleration Accelerator architectures Engines Graphics Hardware Power supplies Rendering (computer graphics) Silicon Sun Workstations |
title | Software in silicon: the methodology behind Sun's GX graphics accelerator architecture |
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