A Floating CDAC architecture for high-resolution and low-power SAR A/D converter

A novel analog-to-digital converter (ADC) architecture based on the principle of successive approximation register (SAR) is described. An algorithm is developed, which allows the conversion of high voltage input signals with a low voltage analog core and without a significant attenuation of the inpu...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	Wickmann, A., Ohnhauser, F.
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	ADC analog-to-digital converters CMOS analog integrated circuits high-resolution Integrated circuits low-noise low-power MOS devices SAR Signal to noise ratio successive approximation register
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