A Floating CDAC architecture for high-resolution and low-power SAR A/D converter

A novel analog-to-digital converter (ADC) architecture based on the principle of successive approximation register (SAR) is described. An algorithm is developed, which allows the conversion of high voltage input signals with a low voltage analog core and without a significant attenuation of the input signal. With this technique the Signal-to-Noise Ratio (SNR) can be improved by up to 10 dB at constant power consumption, or the power dissipation of the ADC can be reduced at constant SNR value. Design considerations and simulation results are presented.