Radiation hardened SOI CMOS and 1M SRAM

Radiation hardened SOI CMOS and 1M SRAM

Describes 2M rad(SiO/sub 2/) radiation hardened partially depleted SOI CMOS technology used to fabricate a 1M SRAM on full dose SIMOX (Separation by IMplantation of OXygen) wafers with an oxygen ion dose of 1.7/spl times/10/sup 18//cm/sup 2/ at 190 keV. They were annealed by Honeywell at 1325 /spl d...

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Bibliographische Detailangaben
Hauptverfasser: Fechner, P.S., Dougal, G.D., Sullwold, J.G., Swanson, R., Shaw, G.A., Liu, S.T., Yue, C.S.
Format: Tagungsbericht
Sprache:eng
Schlagworte:
CMOS process
CMOS technology
Leakage current
MOS devices
MOSFETs
Radiation hardening
Random access memory
Temperature distribution
Testing
Threshold voltage
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Beschreibung
Zusammenfassung:Describes 2M rad(SiO/sub 2/) radiation hardened partially depleted SOI CMOS technology used to fabricate a 1M SRAM on full dose SIMOX (Separation by IMplantation of OXygen) wafers with an oxygen ion dose of 1.7/spl times/10/sup 18//cm/sup 2/ at 190 keV. They were annealed by Honeywell at 1325 /spl deg/C resulting in buried oxide thickness of approximately 370 nm and post CMOS processing silicon thickness of approximately 190 nm. Prior to processing, the SIMOX wafers are screened to achieve surface defect density of
ISSN:1078-621X
2577-2295
DOI:10.1109/SOI.1997.634988