A CMOS LDO regulator with high PSR using Gain Boost-Up and Differential Feed Forward Noise Cancellation in 65nm process

A 65nm CMOS Low Drop-Out (LDO) Regulator is presented employing Gain Boost-Up and Differential Feed Forward Noise Cancellation (DFFNC) to maximize the Power Supply Rejection. The gain boost-up consists of both negative feedback and positive feedback in the error amplifier. With a 1.2V supply voltage, this LDO regulator has a 200mV drop-out voltage and the ability to handle a maximum 25mA load current. The measurement results show a -47dB PSR ratio up to 10MHz and 0.8% of load regulation for the full load current change.