$A low power low phase noise fractional-N synthesizer with linearization and mismatch noise shaping techniques for sub-GHz multi-band transceiver with narrow channel spacing$

A low power low phase noise fractional-N synthesizer with linearization and mismatch noise shaping techniques for sub-GHz multi-band transceiver with narrow channel spacing

A fractional-N frequency synthesizer with a linearized phase-frequency detector and noise shaping of phase mismatch is presented. These techniques lead to spurious free operation over a wide frequency range (133-960M), and 15dB close in phase noise improvement. The core PLL consumes 15mW in 180nm CM...

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Bibliographische Detailangaben
Hauptverfasser:	Blank, T. R., Roine, P. T., Marienborg, J. T., Chakraborty, S., Ackermann, J., Coleman, E. P., Zolnier, J. A., Bulla, C., Kristoffersen, P., Budziak, W. A., Seem, P., Faison, K., Kallerud, T., Nettum, A., Chiang-Hua Yeh
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Charge pumps Fractional N PLL Linearized PFD low-power Multi-band narrow channel spacing Noise shaping Phase frequency detector Phase locked loops phase mismatch Phase noise Quantization Voltage-controlled oscillators
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Beschreibung
Zusammenfassung:	A fractional-N frequency synthesizer with a linearized phase-frequency detector and noise shaping of phase mismatch is presented. These techniques lead to spurious free operation over a wide frequency range (133-960M), and 15dB close in phase noise improvement. The core PLL consumes 15mW in 180nm CMOS and provides phase noise better than -94dBc/Hz@1kHz from a 924MHz carrier.
ISSN:	1930-8833 2643-1319
DOI:	10.1109/ESSCIRC.2012.6341292