Advancing high performance heterogeneous integration through die stacking
This paper describes the industry's first heterogeneous Stacked Silicon Interconnect (SSI) FPGA family (3D integration). Each device is housed in a low-temperature co-fired ceramic (LTCC) package for optimal signal integrity. Inside the package, a heterogeneous IC stack delivers up to 2.78Tb/s...
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Format: | Tagungsbericht |
Sprache: | eng ; jpn |
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Zusammenfassung: | This paper describes the industry's first heterogeneous Stacked Silicon Interconnect (SSI) FPGA family (3D integration). Each device is housed in a low-temperature co-fired ceramic (LTCC) package for optimal signal integrity. Inside the package, a heterogeneous IC stack delivers up to 2.78Tb/s transceiver bandwidth. The resulting bandwidth is approximately three times that achievable in a monolithic solution. Mounted on a passive silicon interposer with through-silicon vias (TSVs), the heterogeneous IC stack comprises FPGA ICs with 13.1-Gb/s transceivers and dedicated analog ICs with 28-Gb/s transceivers. Optimization took place concurrently on multiple facets of the design which were necessary to successfully implement the 3-D integration. In particular, this paper outlines the choices that were made in terms of package substrate material and interposer resistivity in order to optimize 28Gb/s system channel characteristics. These choices were validated through extensive electrical simulation and test chip correlation. In addition, this paper describes the design and timing verification of inter-die interconnects, an area that the electronic design automation industry had not yet fully addressed. This paper further describes 3D thermal-mechanical modeling and analysis for package reliability. The modeling was performed to address package coplanarity issues and stresses imposed by the interposer on the active dice, the low-k dielectric material, the micro-bumps and the C4 attach. The results indicate heterogeneous stacked-silicon (3D) integration is a reliable method to build very high-bandwidth multi-chip devices that exceed current monolithic capabilities. |
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ISSN: | 1930-8833 2643-1319 |
DOI: | 10.1109/ESSCIRC.2012.6341246 |