Design and verification of integrated inductors in CMOS

Design and verification of integrated inductors in CMOS

The design and verification of several monolithic inductor structures is presented. Based on the measurement results of proof-of-concept prototypes in 65 nm CMOS, the inductance (L) and quality factor (Q) of these structures are analyzed both qualitatively and quantitatively. Also, a closed-form app...

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Bibliographische Detailangaben
Hauptverfasser: Molavi, R., Mirabbasi, S., Djahanshahi, H.
Format: Tagungsbericht
Sprache:eng
Schlagworte:
CMOS integrated circuits
CMOS integrated inductors
Inductance
inductor verification
Inductors
Metals
Monolithic inductors
Q factor
Resistance
series peaking
Spirals
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Beschreibung
Zusammenfassung:The design and verification of several monolithic inductor structures is presented. Based on the measurement results of proof-of-concept prototypes in 65 nm CMOS, the inductance (L) and quality factor (Q) of these structures are analyzed both qualitatively and quantitatively. Also, a closed-form approximation for the inductance of vertical spirals is presented and the results are applied to design a compact inductor for serie-speaking at the input of an impedance-matched amplifier.
ISSN:0840-7789
2576-7046
DOI:10.1109/CCECE.2012.6335019