Design and implementation of soft-edge flip-flops for x86-64 AMD microprocessor modules

This paper presents the design and implementation of a family of high-performance soft-edge flip-flops (SEF) used in AMD products with core modules code-named "Bulldozer." We highlight the benefits of the SEF and introduce a new method for comparing flip-flop designs in the presence of clock jitter. We describe an area-efficient level-sensitive scan design (LSSD) implementation in conjunction with supporting clock-gating circuitry for stand-by power reduction. We compare different SEF topologies along with flip-flops from previous designs.