A 12b 200MS/s frequency scalable zero-crossing based pipelined ADC in 55nm CMOS

A 12-bit 200MS/s zero-crossing based pipeline ADC is presented. A coarse phase followed by a level-shifted fine phase is employed for higher accuracy. To enable high frequency operation, sub-ADC flash comparators are strobed immediately after the coarse phase. The ADC occupies 0.276mm 2 in 55nm CMOS...

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Hauptverfasser: Soon-Kyun Shin, Rudell, J. C., Daly, D. C., Munoz, C. E., Dong-Young Chang, Gulati, K., Hae-Seung Lee, Straayer, M. Z.
Format: Tagungsbericht
Sprache:eng
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Beschreibung
Zusammenfassung:A 12-bit 200MS/s zero-crossing based pipeline ADC is presented. A coarse phase followed by a level-shifted fine phase is employed for higher accuracy. To enable high frequency operation, sub-ADC flash comparators are strobed immediately after the coarse phase. The ADC occupies 0.276mm 2 in 55nm CMOS and dissipates 28.5mW. 62.5dB SNDR and 78.6dBc SFDR with a 99.6MHz input signal at 200MS/s are achieved for a FOM of 131fJ/step. The reference buffer, bias circuitry, and digital error correction circuits are all implemented on chip.
ISSN:0886-5930
2152-3630
DOI:10.1109/CICC.2012.6330697