A 5-Gbps 1.7 pJ/bit ditherless CDR with optimal phase interval detection

Dithering in bang-bang controlled CDRs poses conflicting requirements on the phase adjustment resolution as one tries to maximize the tracking bandwidth and minimize jitter. A novel phase interval detector that looks for a phase interval enclosing the desired lock point is shown to find the optimal...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	Myeong-Jae Park, Hanseok Kim, Seuk Son, Jaeha Kim
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Clocks CMOS integrated circuits Detectors Jitter Phase locked loops Prototypes Timing
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