A 5-Gbps 1.7 pJ/bit ditherless CDR with optimal phase interval detection

Dithering in bang-bang controlled CDRs poses conflicting requirements on the phase adjustment resolution as one tries to maximize the tracking bandwidth and minimize jitter. A novel phase interval detector that looks for a phase interval enclosing the desired lock point is shown to find the optimal phase that minimizes the timing error without dithering. A digitally-controlled, phase-interpolating DLL-based CDR fabricated in 65nm CMOS demonstrates that it can achieve low jitter of 41-mUI p-p with a coarse phase adjustment step of 0.11-UI, while dissipating only 8.4mW at 5Gbps. In addition, a digitally-controlled in-situ measurement circuit that can characterize the CDR's jitter tolerance is presented.